diff --git a/tests/test_reference_runs/callab_tests.py b/tests/test_reference_runs/callab_tests.py
index c27e341af9624427c5b9d166119d1d8bb669d2f7..0022c36987996efc317bb67ec6c71107c95fb59b 100644
--- a/tests/test_reference_runs/callab_tests.py
+++ b/tests/test_reference_runs/callab_tests.py
@@ -13,6 +13,7 @@ automated_test_config = {
             "slurm-mem": "750",
             "sequences": "0",
             "rel-gain": True,
+            "n-cores-files": 2,
             "ctrl-source-template": "{}/MDL/FPGA_COMP",
         },
         "reference-folder": "{}/{}/{}",
@@ -47,6 +48,7 @@ automated_test_config = {
             "karabo-id": "SPB_DET_AGIPD1M-1",
             "slurm-mem": "9018",  # Original run: "750",
             "sequences": "0",
+            "n-cores-files": 2,
             "ctrl-source-template": "{}/MDL/FPGA_COMP",
         },
         "reference-folder": "{}/{}/{}",
@@ -81,6 +83,7 @@ automated_test_config = {
             "karabo-id": "MID_DET_AGIPD1M-1",
             "slurm-mem": "750",
             "sequences": "0,1",
+            "n-cores-files": 2,
             "ctrl-source-template": "{}/MDL/FPGA_COMP",
         },
         "reference-folder": "{}/{}/{}",
@@ -102,6 +105,7 @@ automated_test_config = {
             "slurm-mem": "750",
             "sequences": "0,1",
             "ctrl-source-template": "{}/MDL/FPGA_COMP",
+            "n-cores-files": 2,
             "sequences-per-node": 1,
         },
         "reference-folder": "{}/{}/{}",
@@ -122,6 +126,7 @@ automated_test_config = {
             "karabo-id": "MID_DET_AGIPD1M-1",
             "slurm-mem": "750",
             "sequences": "0,1",
+            "n-cores-files": 2,
             "ctrl-source-template": "{}/MDL/FPGA_COMP",
         },
         "reference-folder": "{}/{}/{}",
@@ -155,6 +160,7 @@ automated_test_config = {
             "karabo-id-control": "HED_EXP_AGIPD500K2G",
             "karabo-id": "HED_DET_AGIPD500K2G",
             "slurm-mem": "750",
+            "n-cores-files": 2,
             "sequences": "0,1",
             "ctrl-source-template": "{}/MDL/FPGA_COMP",
         },