diff --git a/notebooks/AGIPD/AGIPD_Correct_and_Verify.ipynb b/notebooks/AGIPD/AGIPD_Correct_and_Verify.ipynb
index b3043673fe3100c0c78d70bb069a7d5cd988849c..5a257ef4429937a90224c88bf971bc19a729c5c1 100644
--- a/notebooks/AGIPD/AGIPD_Correct_and_Verify.ipynb
+++ b/notebooks/AGIPD/AGIPD_Correct_and_Verify.ipynb
@@ -481,18 +481,18 @@
     "        else:\n",
     "            # TODO: replace with proper retrieval (as done in pre-correction)\n",
     "            when = agipd_corr.initialize_from_db(\n",
-    "                karabo_id,\n",
-    "                k_da,\n",
-    "                cal_db_interface,\n",
-    "                creation_time,\n",
-    "                mem_cells_db,\n",
-    "                bias_voltage,\n",
-    "                photon_energy,\n",
-    "                gain_setting,\n",
-    "                acq_rate,\n",
-    "                integration_time,\n",
-    "                mod,\n",
-    "                False,\n",
+    "                karabo_id=karabo_id,\n",
+    "                karabo_da=k_da,\n",
+    "                cal_db_interface=cal_db_interface,\n",
+    "                creation_time=creation_time,\n",
+    "                memory_cells=mem_cells_db,\n",
+    "                bias_voltage=bias_voltage,\n",
+    "                photon_energy=photon_energy,\n",
+    "                gain_setting=gain_setting,\n",
+    "                acquisition_rate=acq_rate,\n",
+    "                integration_time=integration_time,\n",
+    "                module_idx=mod,\n",
+    "                only_dark=False,\n",
     "            )\n",
     "    except Exception as e:\n",
     "        err = f\"Error: {e}\\nError traceback: {traceback.format_exc()}\"\n",
diff --git a/src/cal_tools/agipdlib.py b/src/cal_tools/agipdlib.py
index 7e3f3353cd2923033d3dcbf3a672aeaafd83d3e4..94a908fe52ff8911dc839ee6f195e7feea8b75d6 100644
--- a/src/cal_tools/agipdlib.py
+++ b/src/cal_tools/agipdlib.py
@@ -169,7 +169,7 @@ def get_integration_time(fname: str, h5path_ctrl: str) -> int:
     """Read integration time from the FPGA device.
 
     The integration time is specified as an integer number of clock
-    cylces each spanning ~9ns. The default (and legacy) value is 12.
+    cycles each spanning ~9ns. The default (and legacy) value is 12.
 
     :param fname: path to file with control information
     :param h5path_ctrl: path to control information inside the file