From 99c36978e281d4ba763bca301dc9ab4ee0cd4eb8 Mon Sep 17 00:00:00 2001
From: Cyril Danilevski <cyril.danilevski@xfel.eu>
Date: Wed, 16 Sep 2020 15:21:20 +0200
Subject: [PATCH] Get detector bias voltage from file

---
 cal_tools/cal_tools/agipdlib.py               | 26 ++++++++++++++++++-
 .../Characterize_AGIPD_Gain_Darks_NBC.ipynb   |  4 ++-
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/cal_tools/cal_tools/agipdlib.py b/cal_tools/cal_tools/agipdlib.py
index 18c6560bc..bafdbe3ae 100644
--- a/cal_tools/cal_tools/agipdlib.py
+++ b/cal_tools/cal_tools/agipdlib.py
@@ -61,7 +61,7 @@ def get_acq_rate(slow_paths: Tuple[str, str],
     fast_data_file, karabo_id, module = fast_paths
     fast_data_file = Path(fast_data_file)
     if fast_data_file.exists():
-        fast_data_path = f'INSTRUMENT/{karabo_id}/DET/{module}CH0:xtdf/image/pulseId'
+        fast_data_path = f'INSTRUMENT/{karabo_id}/DET/{module}CH0:xtdf/image/pulseId'  # noqa
         with h5py.File(fast_data_file) as fin:
             if fast_data_path in fin:
                 pulses = np.squeeze(fin[fast_data_path][1:3])
@@ -110,6 +110,30 @@ def get_gain_setting(fname: str, h5path_ctrl: str) -> int:
             raise ValueError('Could not derive gain setting from setupr and patternTypeIndex')  # noqa
 
 
+def get_bias_voltage(fname: str, karabo_id_control: str,
+                     module: Optional[int] = 0) -> int:
+    """Read the voltage information from the FPGA device of module 0.
+
+    Different modules may operate at different voltages. In practice, they all
+    operate at the same voltage. As such, it is okay to read a single module's
+    value.
+
+    This value is read from slow data.
+
+    If the file cannot be accessed, an OSError will be raised.
+    If the hdf5 path cannot be accessed, None will be returned.
+
+    :param fname: path to slow data file with control information
+    :param karabo_id: The detector Karabo id, for creating the hdf5 path
+    :param module: defaults to module 0
+    :return: voltage, a uint16
+    """
+    voltage_path = f'/CONTROL/{karabo_id_control}/FPGA/M_{module}/highVoltage/actual/value'  # noqa
+    with h5py.File(fname, "r") as fin:
+        if voltage_path in fin:
+            return fin[voltage_path][0]
+
+
 class AgipdCorrections:
 
     def __init__(self, max_cells, max_pulses,
diff --git a/notebooks/AGIPD/Characterize_AGIPD_Gain_Darks_NBC.ipynb b/notebooks/AGIPD/Characterize_AGIPD_Gain_Darks_NBC.ipynb
index 160b8ca6a..8f377fe52 100644
--- a/notebooks/AGIPD/Characterize_AGIPD_Gain_Darks_NBC.ipynb
+++ b/notebooks/AGIPD/Characterize_AGIPD_Gain_Darks_NBC.ipynb
@@ -112,7 +112,7 @@
     "from cal_tools.plotting import (create_constant_overview,\n",
     "                                plot_badpix_3d, show_processed_modules,\n",
     "                                show_overview)\n",
-    "from cal_tools.agipdlib import get_gain_setting\n",
+    "from cal_tools.agipdlib import get_bias_voltage, get_gain_setting\n",
     "\n",
     "# make sure a cluster is running with ipcluster start --n=32, give it a while to start\n",
     "from ipyparallel import Client\n",
@@ -222,6 +222,8 @@
     "h5path = h5path.format(karabo_id, receiver_id)\n",
     "h5path_idx = h5path_idx.format(karabo_id, receiver_id)\n",
     "\n",
+    "bias_voltage = get_bias_voltage(control_names[0], karabo_id_control)\n",
+    "\n",
     "print(\"Parameters are:\")\n",
     "print(f\"Proposal: {prop}\")\n",
     "print(f\"Memory cells: {mem_cells}/{max_cells}\")\n",
-- 
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