From f4807d4bc037cdbf4a8805651dd1263865490f06 Mon Sep 17 00:00:00 2001 From: Cyril Danilevski <cyril.danilevski@xfel.eu> Date: Fri, 14 Feb 2025 20:21:37 +0100 Subject: [PATCH] Add channels for all 4 modules in DEPFET quadrant --- powerproc.cpp | 50 ++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/powerproc.cpp b/powerproc.cpp index 3264c4c..1dbfd25 100644 --- a/powerproc.cpp +++ b/powerproc.cpp @@ -8,25 +8,55 @@ PowerProcedure::PowerProcedure(const IPAddress& ipAddr) stages[0].name = "ASICS"; stages[0].type = SWITCH; - stages[0].size = 9; - stages[0].channels = new int[stages[0].size]{508, 708, 502, 503, 504, 501, 507, 607, 608}; + stages[0].size = 15; + stages[0].channels = new int[stages[0].size]{ + 508, 708, // MBJT + 503, 504, // AM, RB + 502, 506, 602, 606, // RB + 501, 505, 601, 605, // IOB + 507, 607, 608 // IOBA + }; stages[1].name = "HV"; stages[1].type = SWITCH; - stages[1].size = 10; - stages[1].channels = new int[stages[1].size]{1, 2, 101, 103, 102, 104, 105, 106, 107, 108}; + stages[1].size = 40; + stages[1].channels = new int[stages[1].size]{ + 1, 2, 3, 4, 5, 6, 7, 8, // IS + 101, 103, 102, 104, // M1 RING1 + 113, 114, 115, 116, // M2 RING1 + 213, 214, 215, 216, // M3 RING1 + 201, 203, 202, 204, // M4 RING1 + 105, 106, 107, 108, // M1 BACK + 109, 110, 111, 112, // M2 BACK + 209, 210, 211, 212, // M3 BACK + 205, 206, 207, 208, // M4 BACK + }; stages[2].name = "ISVOLTAGE"; stages[2].type = VOLTAGE; - stages[2].size = 2; - stages[2].channels = new int[stages[2].size]{1, 2}; - stages[2].onValue = new float[stages[2].size]{10, 10}; - stages[2].offValue = new float[stages[2].size]{2.5, 2.5}; + stages[2].size = 8; + stages[2].channels = new int[stages[2].size]{ + 1, 2, // M1 + 3, 4, // M2 + 5, 6, // M3 + 7, 8 // M4 + }; + stages[2].onValue = new float[stages[2].size]{10, 10, 10, 10, 10, 10, 10, 10}; + stages[2].offValue = new float[stages[2].size]{2.5, 2.5, 2.5, 2.5, 2.5, 2.5, 2.5, 2.5}; stages[3].name = "PLCSOURCE"; stages[3].type = SWITCH; - stages[3].size = 9; - stages[3].channels = new int[stages[3].size]{701, 801, 802, 803, 804, 301, 302, 303, 304}; + stages[3].size = 36; + stages[3].channels = new int[stages[3].size]{ + 701, 801, 802, 803, 804, // M1 PLC + 702, 805, 806, 807, 808, // M2 PLC + 703, 901, 902, 903, 904, // M3 PLC + 704, 905, 906, 907, 908, // M4 PLC + 301, 302, 303, 304, // M1 SG + 305, 306, 307, 308, // M2 SG + 401, 402, 403, 404, // M3 SG + 405, 406, 407, 408, // M4 SG + }; } PowerProcedure::~PowerProcedure() { -- GitLab